As electronic devices increase in complexity, data transfer and processing within these devices require greater coordination. One method to coordinate the data transfer and processing in these devices is clocking. Clocking involves periodic signals that synchronize operations in a device.
A potential problem in clocked systems is skew. Skew refers to two or more signals that lose time reference with respect to each other, therefore frustrating synchronization. Skew may be introduced at transmission time or more likely because of mismatches of interconnect/trace length between transmitting and receiving agents. FIG. 1 illustrates different trace lengths that would likely result in skew.
One solution for skew is lane to lane trace-matching. As I/O transfer speeds continue to increase, trace mismatches between various lanes result in an increasing number of bit cells worth of skew and misalignment. Therefore, trace-matching of interconnects for multiple lanes is tedious, particularly given routing congestions and obstructions that may be present. Sometimes trace-matching is not feasible.
Deskewing provides another approach to counter skewing. Communication systems employing multiple channels or lanes carrying data with forwarded/embedded clock information must have some means of deskewing the received information before further data processing can be done. Deskewing generally involves the receiving end negating skew between involved communication lanes. Deskewing therefore allows data streams to regain timing and phase relationships with respect to each other.
Lane-to-lane skew has conventionally been cancelled at the core/link-layer. However, the technique introduces a high latency penalty, since the link-layer for a typical serial I/O interface runs slower than the I/O interface, typically by a factor of 10x˜20x, and employs area intensive elastic buffers.